A formal verification method of scheduling in high-level synthesis

Karfa, C., Mandal, Chittaranjan, Sarkar, Dipankar, Pentakota, Satyam R. and Reade, Chris (2006) A formal verification method of scheduling in high-level synthesis. In: 7th International Symposium on Quality Electronic Design; 27-29 Mar 2006, San Jose, USA. ISBN 0769525237

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Item Type: Conference or Workshop Item (Paper)
Event Title: 7th International Symposium on Quality Electronic Design
Uncontrolled Keywords: Formal methods
Research Area: Computer science and informatics
Faculty, School or Research Centre: Faculty of Business and Law
Faculty of Business and Law > Kingston Business School (Informatics and Operations Management) (until July 2013)
Depositing User: Robert Elves
Date Deposited: 23 Sep 2008
Last Modified: 03 Aug 2010 15:04
URI: http://eprints.kingston.ac.uk/id/eprint/2035

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