Karfa, C., Mandal, Chittaranjan, Sarkar, Dipankar, Pentakota, Satyam R. and Reade, Chris (2006) A formal verification method of scheduling in high-level synthesis. In: 7th International Symposium on Quality Electronic Design; 27-29 Mar 2006, San Jose, USA. ISBN 0769525237
Official URL: http://dx.doi.org/10.1109/ISQED.2006.10
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