Karfa, Chandan, Mandal, Chittaranjan, Sarkar, Dipankar, Pentakota, S.R. and Reade, Chris (2006) Verification of scheduling in high-level synthesis. In: IEEE Computer Society Annual Syposium on Emerging VLSI Technologies and Architectures 2006; 2-3 Mar 2006, Karlsruhe, Germany. ISBN 0769525334
Full text not available from this archive.
Official URL: http://dx.doi.org/10.1109/ISVLSI.2006.93
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Event Title: | IEEE Computer Society Annual Syposium on Emerging VLSI Technologies and Architectures 2006 |
| Uncontrolled Keywords: | Formal methods |
| Research Area: | Computer science and informatics |
| Faculty, School or Research Centre: | Faculty of Business and Law Faculty of Business and Law > Kingston Business School (Informatics and Operations Management) |
| Depositing User: | Robert Elves |
| Date Deposited: | 23 Sep 2008 |
| Last Modified: | 03 Aug 2010 14:57 |
| URI: | http://eprints.kingston.ac.uk/id/eprint/2021 |
Actions (Repository Editors)
 |
Item Control Page |