Karfa, Chandan, Mandal, Chittaranjan, Sarkar, Dipankar, Pentakota, S.R. and Reade, Chris (2006) Verification of scheduling in high-level synthesis. In: IEEE Computer Society Annual Syposium on Emerging VLSI Technologies and Architectures 2006; 2-3 Mar 2006, Karlsruhe, Germany. ISBN 0769525334
Official URL: http://dx.doi.org/10.1109/ISVLSI.2006.93
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